This invention relates to a fullwave rectifier circuit comprising a signal input for receiving an input signal current to be rectified, which signal input is coupled to a signal output via a rectifier stage, said stage comprising a semiconductor junction for conduction of the input signal during one half-cycle of the current and a first current mirror for mirroring the input signal current during the other half-cycle of the current to the signal output, a differential amplifier having an input coupled to the input of the rectifier stage and having its output negatively fed back via a driver stage to the input of the rectifier stage, and a current source for supplying the supply currents of the driver stage and the first current mirror.
Such a full wave rectifier circuit forms a part of the known integrated circuit TEA 0652. FIG. 1 shows a circuit diagram of this circuit. In this diagram a differential amplifier 1 has an input connected to a reference voltage V.sub.R and has its output connected to the input of a driver stage. The driver stage comprises an npn transistor Q.sub.16 whose emitter is connected to the negative supply voltage terminal and whose collector is connected to the base of a transistor Q.sub.11, whose emitter is connected to a further input of the differential amplifier 1 to provide negative feedback. This input, i.e. the emitter of the transistor Q.sub.11, receives the signal current to be rectified from a signal input 2. In addition to the transistor Q.sub.11 the rectifier stage comprises a current mirror 3, which has its input connected to the input 2 and which has its output connected to the collector of the transistor Q.sub.11, which constitutes the rectifier output or is coupled thereto.
The supply current for the current mirror 3 is furnished by a direct current source which is connected to the collector of the transistor Q.sub.16 via a diode Q.sub.15. This, the direct current source supplies both the supply current for the current mirror 3 (which supply current corresponds to the sum of the currents flowing into and out of the current mirror) and the supply current for the driver stage Q.sub.15, Q.sub.16.
The prior-art circuit operates as follows. If the signal current applied to the input 2 has a positive polarity the signal current will flow to the rectifier output 5 of the circuit via the collector emitter path of the transistor Q.sub.11. For this polarity of the input current no current will flow in the current mirror 3. In the case of a negative polarity the signal current flows to the positive supply voltage terminal via the input of the current mirror 3 and the current source 4, causing a current of the same polarity as during the positive half-cycle to flow from the output of the current mirror 3 to the output 5. This results in current half-cycles of the same polarity appearing on the output 5 in the case of an alternating polarity of the current at the input 2, which corresponds to full wave rectification.
The current supplied by the current source 4 should be at least slightly larger than the current supplied by the current mirror 3 in the case of a signal current of negative polarity and maximal amplitude, in order to ensure that the driver stage Q.sub.15, Q.sub.16 does not become currentless and that the negative feedback loop comprising the differential amplifier 1, the driver stage and the transistor Q.sub.11 remains operative, which loop pulls the potential on the two differential amplifier inputs towards the same value (i.e. the reference voltage V.sub.R). In the case of a positive polarity of the signal current, the entire current supplied by the direct current source 4 flows via the driver stage Q.sub.15 and Q.sub.16. Consequently, this current is substantially larger than during the negative half-cycle and requires a correspondingly large base current. Such a base current implies a voltage offset on the input of the differential amplifier, i.e. in the case of a positive polarity of the input current the potentials on the two inputs of the differential amplifier can no longer be identical. This voltage offset results in unequal half cycles (of the same polarity) appearing on the output 5 of the rectifier stage, in particular in the case of small signal currents having equal current half cycles on the input 2. This distortion is undesirable, in particular if the rectified signal is used as a control signal in a rapidly responding control circuit.